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m28f256 256 kbit (32kb x8, bulk) flash memory august 1998 1/20 ai00688b 15 a0-a14 w dq0-dq7 v pp v cc m28f256 g e v ss 8 figure 1. logic diagram 5v 10% supply voltage 12v programming voltage fast access time: 90ns byte programming time: 10 m s typical electrical chip erase in 1s range low power consumption standby current: 5 m a typical 10,000 erase/program cycles integrated erase/program stop timer 20 years data retention defectivity below 1ppm/year electronic signature manufacturer code: 20h device code: a8h description the m28f256 flash memory is a non-volatile memory that may be erased electrically at the chip level and programmed by byte. it is organised as 32 kbytes of 8 bits. it uses a command register architectureto select the operatingmodes and thus provides a simple microprocessor interface. the device is offered in pdip32 and plcc32 pack- ages. a0-a14 address inputs dq0-dq7 data inputs / outputs e chip enable g output enable w write enable v pp program supply v cc supply voltage v ss ground table 1. signal names plcc32 (c) 32 1 pdip32 (b)
ai00690 nc a13 a10 dq5 17 a1 a0 dq0 dq1 dq2 dq3 dq4 a7 a4 a3 a2 a6 a5 9 w a8 1 nc a9 dq7 a12 a14 32 v pp v cc m28f256 nc a11 dq6 g e 25 v ss figure 2b. lcc pin connections a1 a0 dq0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 dq7 a14 a11 g e dq5 dq1 dq2 dq3 v ss dq4 dq6 nc w nc a12 v pp v cc nc ai00689 m28f256 8 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 figure 2a. dip pin connections warning: nc = not connected warning: nc = not connected symbol parameter value unit t a ambient operating temperature (4) 40 to 125 c t bias temperature under bias 50 to 125 c t stg storage temperature 65 to 150 c v io (2, 3) input or output voltages 0.6 to v cc + 0.5 v v cc supply voltage 0.6 to 7 v v (a9, rp) (2) a9, rp voltage 0.6 to 13.5 v v pp (2) program supply voltage, during erase or programming 0.6 to 14 v notes: 1. except for the rating ooperating temperature rangeo, stresses above those listed in the table oabsolute maximum ratingso may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. 2. minimum voltage may undershoot to 2v during transition and for less than 20ns. 3. maximum voltage may overshoot to 7v during transition and for less than 20ns. 4. depends on range. table 2. absolute maximum ratings device operation the m28f256 flash memory employs a technol- ogy similar to a 256k eprom but adds to the device functionality by providing electrical erasure and programming. these functions are managed by a command register. the functions that are addressed via the command register depend on the voltage applied to the v pp , program voltage, input. when v pp is less than or equal to 6.5v, the command register is disabled and m28f256 func- tions as a read only memory providing operating modes similar to an eprom (read, output dis- able, electronic signature read and standby). when v pp is raised to 12v the command register is enabled and this provides, in addition, erase and program operations. 2/20 m28f256
read only modes, v pp 6.5v for all read only modes, except standby mode, the write enable input w should be high. in the standby mode this input is 'don't care'. read mode. the m28f256 has two enable inputs, e and g, both of which must be low in order to output data from the memory. the chip enable (e) is the power control and should be used for device selection. output enable (g) is the output control and should be used to gate data on to the output, independant of the device selection. standby mode. in the standby mode the maxi- mum supply current is reduced to 100 m a. the device is placed in the standby mode by applying a high to the chip enable (e) input. when in the standbymode the outputs are in a high impedance state, independant of the output enable (g) input. output disable mode . when the output enable (g) is high the outputs are in a high impedance state. electronicsignature mode. this mode allows the read out of two binary codes from the device which identify the manufacturer and device type. this mode is intended for use by programming equip- ment to automatically select the correct erase and programming algorithms. the electronic signature mode is active when a high voltage (11.5v to 13v) is applied to addressline a9 with e and g low. with a0 low the output data is the manufacturer code, when a0 is high the output is the device type code. all other address lines should be maintained low while reading the codes. the electronic signature may also be accessed in read/write modes. read/write modes, 11.4v v pp 12.6v when v pp is high both read and write operations may be performed. these are defined by the con- tents of an internal command register. commands may be written to this register to set-up and exe- cute, erase, erase verify, program, programverify and reset modes. each of these modes needs 2 cycles. every mode starts with a write operation to set-up the command,this is followed by either read or write operations. the device expects the first cycle to be a write operation and does not corrupt data at any location in memory. read mode is set-up with one cycle only and may be followed by any number of read operations to output data. electronic signature read mode is set-up with one cycle and followed by a read cycle to output the manufacturer or device codes. v pp operation e g w a9 dq0 - dq7 read only v ppl read v il v il v ih a9 data output output disable v il v ih v ih x hi-z standby v ih x x x hi-z electronic signature v il v il v ih v id codes read/write (2) v pph read v il v il v ih a9 data output write v il v ih v il pulse a9 data input output disable v il v ih v ih x hi-z standby v ih x x x hi-z notes: 1. x = v il or v ih 2. refer also to the command table table 3. operations (1) identifier a0 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 hex data manufacturer's code v il 00100000 20h device code v ih 10101000 0a8h table 4. electronic signature 3/20 m28f256
command cycles 1st cycle 2nd cycle operation a0-a14 dq0-dq7 operation a0-a14 dq0-dq7 read 1 write x 00h electronic signature 2 write x 90h read 0000h 20h read 0001h 0a8h setup erase/ 2 write x 20h erase write x 20h erase verify 2 write a0-a14 0a0h read x data output setup program/ 2 write x 40h program write a0-a14 data input program verify 2 write x 0c0h read x data output reset 2 write x 0ffh write x 0ffh note: 1. x = v il or v ih table 5. commands (1) awrite to the command register is made bybringing w low while e is low. the falling edge of w latches addresses, while the rising edge latches data, which are used for those commands that require address inputs, command input or provide data output. the supply voltage v cc and the program voltage v pp can be applied in any order. when the device is powered up or when v pp is 6.5v the contents of the command register default to 00h, thus auto- matically setting-up read operations. in addition a specific command may be used to set the com- mand register to 00h for reading the memory. the system designer may choose to provide a constant high v pp and use the register commands for all operations, or to switch the v pp from low to high only when needing to erase or program the memory. all command register access is inhibited when v cc falls belowthe erase/write lockout volt- age (v lko ) at 2.5v. if the device is deselected during erasure, pro- gramming or verification it will draw active supply currents until the operations are terminated. the device is protected against stress caused by long erase or program times. if the end of erase or programming operations are not terminated by a verify cycle within a maximum time permitted, an internal stop timer automatically stops the opera- tion. the device remains in an inactive state, ready to start a verify or reset mode operation. read mode. the read mode is the default at power up or may be set-up by writing 00h to the command register. subsequent read operations outputdata from the memory. thememory remains in the read mode until a new command is written to the command register. electronic signature mode. in order to select the correct erase and programming algorithms for on- board programming, the manufacturerand devices code may be read directly. it is not neccessary to apply a high voltage to a9 when using the com- mand register. the electronic signature mode is set-up by writing 90h to the command register. the following read cycle, with address inputs 0000h or 0001h, output the manufacturer or device type codes. the command is terminated by writing an- other valid command to the command register (for example reset). read/write modes (cont'd) 4/20 m28f256
erase and erase verify modes. the memory is erased by first programming all bytes to 00h, the erase command then erases them to 0ffh. the erase verify command is then used to read the memory byte-by-byte for a content of 0ffh. the erase mode is set-up by writing 20h to the command register. the write cycle is thenrepeated to start the erase operation. erasure starts on the rising edge of w during this second cycle. erase is followed by an erase verify which reads an ad- dressed byte. erase verify mode is set-up by writing 0a0h to the command register and at the same time supplying the address of the byte to be verified. the rising edge of w during the set-up of the first erase verify mode stops the erase operation. the following read cycle is made with an internally generated margin voltage applied; reading 0ffh indicates that all bits of the addressed byte are fully erased. the whole contents of the memory are verified by repeating the erase verify operation, first writing the set-up code 0a0h with the address of the byte to be verified and then reading the byte contentsin a second read cycle. as the erase algorithm flow chart shows, when the data read during erase verify is not 0ffh, another erase operation is performed and verification con- tinues from the addressof the last verifiedbyte. the command is terminated by writing another valid command to the command register (for example program or reset). input rise and fall times 10ns input pulse voltages 0.45v to 2.4v input and output timing ref. voltages 0.8v to 2v note that output hi-z is defined as the point where data is no longer driven. table 6. ac measurement conditions symbol parameter test condition min max unit c in input capacitance v in =0v 6 pf c out output capacitance v out =0v 12 pf note: 1. sampled only, not 100% tested table 7. capacitance (1) (t a =25 c, f = 1 mhz ) ai00828 1.3v out c l = 100pf c l includes jig capacitance 3.3k w 1n914 device under test figure 4. ac testing load circuit ai00827 2.4v 0.45v 2.0v 0.8v figure 3. ac testing input output waveforms 5/20 m28f256
symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 m a i lo output leakage current 0v v out v cc 10 m a i cc supply current (read) e = v il , f = 6mhz 30 ma i cc1 supply current (standby) ttl e = v ih 1ma supply current (standby) cmos e = v cc 0.2v 100 m a i cc2 (1) supply current (programming) during programming 10 ma i cc3 (1) supply current (program verify) during verify 10 ma i cc4 (1) supply current (erase) during erasure 10 ma i cc5 (1) supply current (erase verify) during erase verify 10 ma i lpp program leakage current v pp v cc 10 m a i pp program current (read or standby) v pp >v cc 200 m a v pp v cc 10 m a i pp1 (1) program current (programming) v pp =v pph , during programming 10 ma i pp2 (1) program current (program verify) v pp =v pph , during verify 10 ma i pp3 (1) program current (erase) v pp =v pph , during erase 5 ma i pp4 (1) program current (erase verify) v pp =v pph , during erase verify 5 ma v il input low voltage 0.5 0.8 v v ih input high voltage ttl 2 v cc + 0.5 v input high voltage cmos 0.7 v cc v cc + 0.5 v v ol output low voltage i ol = 5.8ma (grade 1) 0.45 v i ol = 2.1ma (grade 6) 0.45 v v oh output high voltage cmos i oh = 100 m a 4.1 v i oh = 1ma v cc 0.8 v i oh = 2.5ma (grade 1) v cc 0.8 v output high voltage ttl i oh = 2.5ma 2.4 v v ppl program voltage (read operations) 0 6.5 v v pph program voltage (read/write operations) 11.4 12.6 v v id a9 voltage (electronic signature) 11.5 13 v i id (1) a9 current (electronic signature) a9 = v id 200 m a v lko supply voltage, erase/program lock-out 2.5 v note: 1. not 100% tested. characterisation data available. table 8. dc characteristics (t a = 0 to 70 c, 40 to 85 c or 40 to 125 c; v cc =5v 5% or 5v 10%) 6/20 m28f256
symbol alt parameter test condition m28f256 unit -90 -10 -12 standard interface standard interface standard interface min max min max min max t avav t rc read cycle time e = v il ,g=v il 90 100 120 ns t avqv t acc address valid to output valid e=v il ,g=v il 90 100 120 ns t elqx t lz chip enable low to output transition g=v il 000ns t elqv t ce chip enable low to output valid g=v il 90 100 120 ns t glqx t olz output enable low to output transition e=v il 000ns t glqv t oe output enable low to output valid e=v il 35 40 50 ns t ehqz (1) chip enable high to output hi-z g=v il 0 20 0 30 0 40 ns t ghqz (1) t df output enable high to output hi-z e=v il 0 20 0 30 0 30 ns t axqx t oh address transition to output transition e=v il ,g=v il 000ns note: 1. sampled only, not 100% tested table 9a. read only mode ac characteristics (t a = 0 to 70 c, 40 to 85 c, 40 to 125 c; v cc =5v 5% or 5v 10%; 0v v pp 6.5v) symbol alt parameter test condition m28f256 unit -15 -20 standard interface standard interface min max min max t avav t rc read cycle time e = v il ,g=v il 150 200 ns t avqv t acc address valid to output valid e = v il ,g=v il 150 200 ns t elqx t lz chip enable low to output transition g=v il 00ns t elqv t ce chip enable low to output valid g = v il 150 200 ns t glqx t olz output enable low to output transition e=v il 00ns t glqv t oe output enable low to output valid e = v il 55 60 ns t ehqz (1) chip enable high to output hi-z g = v il 0 55 0 60 ns t ghqz (1) t df output enable high to output hi-z e = v il 0 35 0 40 ns t axqx t oh address transition to output transition e=v il ,g=v il 00ns note: 1. sampled only, not 100% tested table 9b. read only mode ac characteristics ((t a = 0 to 70 c, 40 to 85 c, 40 to 125 c; v cc =5v 5% or 5v 10%; 0v v pp 6.5v) 7/20 m28f256
ai00683 twhgl tvphel valid telqv tehqz tavqv a0-a14 e g dq0-dq7 data out command v pp w taxqx tghqz tglqv read read set-up twlwh twhdx tdvwh tghwl telwl twheh figure 6. read command waveforms ai00682 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz data out a0-a14 e g dq0-dq7 figure 5. read mode ac waveforms 8/20 m28f256
ai00684 twhgl tvphel 0000h-0001h telqv tehqz tavqv a0-a14 e g dq0-dq7 data out command v pp w taxqx tghqz tglqv read manufacturer or device read electronic signature set-up twlwh twhdx tdvwh tghwl telwl twheh figure 7. electronic signature command waveforms program and program verify modes. the pro- grammode is set-up by writing 40h to thecommand register. this is followed by a second write cycle which latches the address and data of the byte to be programmed. the rising edge of w during this second cycle starts the programming operation. programming is followed by a programverify of the data written. program verify mode is set-up by writing 0c0h to the command register. the rising edge of w during the set-up of the program verify mode stops the programming operation. the following read cycle, of the address already latched during program- ming, is made with an internally generated margin voltage applied, reading valid data indicates that all bits have been programmed. reset mode. this command is usedto safelyabort erase or program modes. the reset mode is set-up and performed by writing 0ffh two times to the command register. the command should be followed by writing a valid command to the the command register (for example read). 9/20 m28f256
symbol alt parameter m28f256 unit -90 -10 -12 standard interface standard interface standard interface min max min max min max t vphel v pp high to chip enable low 100 100 100 ns t vphwl v pp high to write enable low 100 100 100 ns t whwh3 t wc write cycle time 90 100 120 ns t avwl t as address valid to write enable low 0 0 0 ns t avel address valid to chip enable low 0 0 0 ns t wlax t ah write enable low to address transition 45 50 60 ns t elax chip enable low to address transition 50 60 80 ns t elwl t cs chip enable low to write enable low 15 15 20 ns t wlel write enable low to chip enable low 0 0 0 ns t ghwl output enable high to write enable low 0 0 0 m s t ghel output enable high to chip enable low 0 0 0 m s t dvwh t ds input valid to write enable high 45 50 50 ns t dveh input valid to chip enable high 35 40 50 ns t wlwh t wp write enable low to write enable high (write pulse) 45 50 60 ns t eleh chip enable low to chip enable high (write pulse) 45 45 70 ns t whdx t dh write enable high to input transition 10 10 10 ns t ehdx chip enable high to input transition 10 10 10 ns t whwh1 duration of program operation 9.5 9.5 9.5 m s t eheh1 duration of program operation 9.5 9.5 9.5 m s t whwh2 duration of erase operation 9.5 9.5 9.5 ms t wheh t ch write enable high to chip enable high 0 0 0 ns t ehwh chip enable high to write enable high 0 0 0 ns t whwl t wph write enable high to write enable low 20 20 20 ns t ehel chip enable high to chip enable low 20 20 20 ns t whgl write enable high to output enable low 6 6 6 m s t ehgl chip enable high to output enable low 6 6 6 m s t avqv t acc addess valid to data output 90 100 120 ns t elqx (1) t lz chip enable low to output transition 0 0 0 ns t elqv t ce chip enable low to output valid 90 100 120 ns t glqx (1) t olz output enable low to output transition 0 0 0 ns t glqv t oe output enable low to output valid 35 45 50 ns t ehqz (1) chip enable high to output hi-z 20 30 50 ns t ghqz (1) t df output enable high to output hi-z 20 30 30 ns t axqx t oh address transition to output transition 0 0 0 ns notes: 1. sampled only, not 100% tested 2. a write is enabled by a valid combination of chip enable (e) and write enable (w). when write is controlled by chip enable (with a chip enable pulse width smaller than write enable), all timings should be measured relative to chip enable waveform. table 10a. read/write mode ac characteristics, w and e controlled (t a = 0 to 70 c, 40 to 85 c or 40 to 125 c; v cc =5v 5% or 5v 10%; v pp = 12v) 10/20 m28f256
symbol alt parameter m28f256 unit -15 -20 standard interface standard interface min max min max t vphel v pp high to chip enable low 100 100 ns t vphwl v pp high to write enable low 100 100 ns t whwh3 t wc write cycle time 150 200 ns t avwl t as address valid to write enable low 0 0 ns t avel address valid to chip enable low 0 0 ns t wlax t ah write enable low to address transition 60 60 ns t elax chip enable low to address transition 80 80 ns t elwl t cs chip enable low to write enable low 20 20 ns t wlel write enable low to chip enable low 0 0 ns t ghwl output enable high to write enable low 0 0 m s t ghel output enable high to chip enable low 0 0 m s t dvwh t ds input valid to write enable high 50 50 ns t dveh input valid to chip enable high 50 50 ns t wlwh t wp write enable low to write enable high (write pulse) 60 60 ns t eleh chip enable low to chip enable high (write pulse) 70 70 ns t whdx t dh write enable high to input transition 10 10 ns t ehdx chip enable high to input transition 10 10 ns t whwh1 duration of program operation 9.5 9.5 m s t eheh1 duration of program operation 9.5 9.5 m s t whwh2 duration of erase operation 9.5 9.5 ms t wheh t ch write enable high to chip enable high 0 0 ns t ehwh chip enable high to write enable high 0 0 ns t whwl t wph write enable high to write enable low 20 20 ns t ehel chip enable high to chip enable low 20 20 ns t whgl write enable high to output enable low 6 6 m s t ehgl chip enable high to output enable low 6 6 m s t avqv t acc addess valid to data output 150 200 ns t elqx (1) t lz chip enable low to output transition 0 0 ns t elqv t ce chip enable low to output valid 150 200 ns t glqx (1) t olz output enable low to output transition 0 0 ns t glqv t oe output enable low to output valid 55 60 ns t ehqz (1) chip enable high to output hi-z 55 60 ns t ghqz (1) t df output enable high to output hi-z 35 40 ns t axqx t oh address transition to output transition 0 0 ns notes: 1. sampled only, not 100% tested 2. a write is enabled by a valid combination of chip enable (e) and write enable (w). when write is controlled by chip enable (with a chip enable pulse width smaller than write enable), all timings should be measured relative to chip enable waveform. table 10b. read/write mode ac characteristics, w and e controlled (t a = 0 to 70 c, 40 to 85 c or 40 to 125 c; v cc =5v 5% or 5v 10%; v pp = 12v) 11/20 m28f256
ai01170 twheh tvphel valid telqv tehqz tavwl a0-a14 e g dq0-dq7 command v pp w twlax tghqz twhwh2 verify read erase set-up twlwh twhdx tdvwh tghwl telwl twheh command twhgl twhwl command twhdx tdvwh data out twhwh3 erase operation twlwh tglqv erase set-up (repeat of 1st cycle) erase verify set-up telwl figure 8. erase set-up and erase verify commands waveforms, w controlled 12/20 m28f256
ai01171 tehwh tvphwl valid tglqv tehqz tavel a0-a14 w g dq0-dq7 command v pp e telax tghqz teheh2 verify read erase set-up teleh tehdx tdveh tghel twlel tehwh command tehgl tehel command tehdx tdveh data out twhwh3 erase operation teleh telqv erase set-up (repeat of 1st cycle) erase verify set-up twlel figure 9. erase set-up and erase verify commands waveforms, e controlled 13/20 m28f256
ai01172 twheh tvphel valid telqv tehqz tavwl a0-a14 e g dq0-dq7 command v pp w twlax tghqz twhwh1 verify read program set-up twlwh twhdx tdvwh tghwl telwl twheh data in twhgl twhwl command twhdx tdvwh data out twhwh3 program operation twlwh tglqv address and data latch program verify set-up telwl twhdx tdvwh telwl twlwh twheh figure 10. program set-up and program verify commands waveforms, w controlled 14/20 m28f256
ai01173 tehwh tvphel valid telqv tehqz tavel a0-a14 g dq0-dq7 command v pp w telax tghqz teheh1 verify read program set-up teleh tehdx tdveh tghel twlel tehwh data in tehgl tehel command tehdx tdveh data out twhwh3 program operation teleh tglqv address and data latch program verify set-up twlel tehdx tdveh twlel teleh tehwh e figure 11. program set-up and program verify commands waveforms, e controlled 15/20 m28f256
program all bytes to 00h ai00687 n=0, addr=0000h last addr erase set-up wait 10ms erase verify latch addr. read data output data ok wait 6 m s ++n addr++ read command v pp = 12v v pp < 6.5v fail v pp < 6.5v, pass yes no yes no yes no limit figure 12. erasing flowchart presto f erase algorithm the presto f erase algorithm guarantees that the device will be erased in a reliable way. the algorithm first programs all bytes to 00h in order to ensure uniform erasure. the programming follows the presto f programming algorithm (see below). erase is set-up by writing 20h to the command register, the erasure is started by repeating this write cycle. erase verify is set-up by writing 0a0h to the command register together with the address of the byte to be verified. the subsequent read cycle reads the data which is compared to 0ffh. erase verify begins at address 0000h and contin- ues to the last address or until the comparison of the data to 0ffh fails. if this occurs, the address of the last byte checked is stored and a new erase operation performed. erase verify then continues from the address of the stored location. presto f program algorithm the presto f programming algorithm applies a series of 10 m s programming pulses to a byte until a correct verify occurs. up to 25 programming operations are allowed for one byte. program is set-up by writing 40h to the command register, the programming is started after the next write cycle which also latches the address and data to be programmed. program verify is set-up by writing 0c0h to the command register, followed by a read cycle and a compare of the data read to the data expected. during program and program verify op- erations a margin mode circuit is activated to guaranteethat the cell is programmed with a safety margin. ai00677 n=0 last addr program verify wait 10 m s program set-up latch addr, data read data output data ok wait 6 m s ++n =25 addr++ read command v pp = 12v v pp < 6.5v fail v pp < 6.5v, pass yes no yes no yes no figure 13. programming flowchart 16/20 m28f256
ordering information scheme for a list of available options (speed, package, etc...) or for further informationon any aspect of this device, please contact the stmicroelectronics sales office nearest to you. speed -90 90 ns -10 100 ns -12 120 ns -15 150 ns -20 200 ns v cc tolerance blank 10% x 5% package b pdip32 c plcc32 temp. range 1 0 to 70 c 3 40 to 125 c 6 40 to 85 c option tr tape & reel packing example: m28f256 -12 x b 1 tr 17/20 m28f256
pdip32 - 32 pin plastic dip, 600 mils width pdip a2 a1 a l b1 b e1 d s e1 e n 1 c a ea eb d2 symb mm inches typ min max typ min max a 5.08 0.200 a1 0.38 0.015 a2 3.56 4.06 0.140 0.160 b 0.38 0.51 0.015 0.020 b1 1.52 0.060 c 0.20 0.30 0.008 0.012 d 41.78 42.04 1.645 1.655 d2 38.10 1.500 e 15.24 0.600 e1 13.59 13.84 0.535 0.545 e1 2.54 0.100 ea 15.24 0.600 eb 15.24 17.78 0.600 0.700 l 3.18 3.43 0.125 0.135 s 1.78 2.03 0.070 0.080 a 0 10 0 10 n32 32 drawing is not to scale 18/20 m28f256
plcc d ne e1 e 1n d1 nd cp b d2/e2 e b1 a1 a r 0.51 (.020) 1.14 (.045) f a2 symb mm inches typ min max typ min max a 2.54 3.56 0.100 0.140 a1 1.52 2.41 0.060 0.095 a2 0.38 0.015 b 0.33 0.53 0.013 0.021 b1 0.66 0.81 0.026 0.032 d 12.32 12.57 0.485 0.495 d1 11.35 11.56 0.447 0.455 d2 9.91 10.92 0.390 0.430 e 14.86 15.11 0.585 0.595 e1 13.89 14.10 0.547 0.555 e2 12.45 13.46 0.490 0.530 e 1.27 0.050 f 0.00 0.25 0.000 0.010 r 0.89 0.035 n32 32 nd 7 7 ne 9 9 cp 0.10 0.004 drawing is not to scale plcc32 - 32 lead plastic leaded chip carrier, rectangular 19/20 m28f256
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 1998 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. 20/20 m28f256

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